Development of computational methods for biomedical data analysis in software and hardware

The topic of this thesis is the development of novel methods of biomedical data analysis in software and hardware. A novel system has been developed for the extraction of second-order statistic texture features from images and video in software and hardware. Additionally, a novel FPGA-based architecture for the calculation of the logarithm function has been developed, which achieves fast operation, high accuracy and low resource utilization. Finally, a novel method for automatic microarray image gridding has been developed, based on the maximization of the margin between consecutive rows or columns of microarray spots. 1 Feature extraction system Texture is an innate property of the natural objects and it is widely used for video content description. The utility of texture feature extraction from video extends to a wide range of advanced modern applications, such as segmentation of objects in image sequences, object recognition and tracking of moving objects. The Gray Level Cooccurrence Matrix (GLCM) features [1] describe the textural image content by encoding the second order statistical properties of texture. These features have been successfully utilized in a number of applications including medical, remote sensing and industrial visual inspection applications. GLCMs encode the gray level spatial dependence based on the estimation of the 2nd order joint-conditional probability density function, which is computed by counting all pairs of pixels of a video frame block at distance d having gray levels i and j at a given direction θ. The cooccurrence matrix can be regarded symmetric if the distribution between opposite directions is ignored, so the usual values of the angular displacement are 0◦, 45◦, 90◦ and 135◦. We have considered four GLCM features [1], namely angular second moment (f1), correlation (f2), inverse difference moment (f3) and entropy (f4), which have been shown to provide high discrimination accuracy. In the following equations, pij is the ijth entry of the cooccurrence matrix, μx, μy, σx, and σy are the means and standard deviations of the marginal probabilities Px(i) and Py(j) obtained by summing up the rows or the columns of matrix pij respectively. ? Dissertation advisor: Dimitris Maroulis, Associate Professor f1 = ∑∑ pij f2 = ∑∑ i · j · pij − μx · μy σx · σy f3 = ∑∑ 1 1 + (i− j)2 · pij f4 = − ∑∑ pij · log pij (1) The above calculations require floating point operations that would result in high FPGA area utilization and low operating frequencies. To implement the calculation of the features efficiently in hardware, we have reformulated the equations by extracting the following five expressions (V1 to V5), where cij is the ijth entry of the unnormalized cooccurrence matrix, Cx(k) is obtained by summing up the rows of matrix cij and L1[i− j] is a small lookup table. In these equations, the operations needed to calculate V1 to V5 are performed exclusively in hardware using integer or fixed point arithmetic. V1 = ∑∑ cij V2 = ∑∑ i · j · cij V3 = ∑∑ cij · L1[i− j] V4 = ∑∑ cij · log2 cij V5 = ∑ C x(k) (2) 1.1 Hardware implementation The hardware implementation is based on a Xilinx XCV2000E-6 FPGA, programmed in VHDL. The architecture of the implemented hardware is illustrated in Fig. 1. The software iteratively feeds the FPGA board with four video frame blocks per iteration. The FPGA reads each block’s pixels, calculates the GLCM of each block and their respective feature vectors for the four directions and a distance of one pixel, and stores them into memory bank 1 and 2. The architecture consists of several units. The control unit coordinates the functions of the other units and handles the communication with the host, whereas the memory controllers handle the transactions between the FPGA and the memory banks. The circular buffers implements a buffering scheme that reads the pixels of the four blocks sequentially at a rate of four pixels per clock cycle and produces pairs of gray level intensities (i, j) for each block and direction considered, at a rate of 20 pixels per cycle. A GLCM calculation unit (GCU) is used for the calculation of the GLCM of a single block for a particular direction. It consists of an n-way set associative array [2] with a capacity of Nc cells and the auxiliary circuitry needed for the calculation of the GLCM. Set associative arrays can be used for efficient storage and retrieval of sparse matrices, with a throughput of one operation per cycle. The set associative array uniquely maps an input pair of 6-bit gray-level intensities (i, j) to an address of the Nc-cell data array, which is implemented using FPGA Block RAMs. The FPGA architecture consists of: & A control unit & Three memory controllers (for memory banks 0, 1 and 2) & A circular buffers unit & Sixteen GLCM calculation units (GCUs) & Four vector calculation units (VCUs) 3.1 Control Unit The control unit coordinates the FPGA functions by generating synchronization signals that coordinate the memory controllers, the circular buffers unit, the GLCM calculation units (GCUs) and the vector calculation units (VCUs). It also handles the communication with the host, by exchanging control and status bytes and by requesting or giving up the ownership of the memory banks. 3.2 Memory Controllers Three memory controllers handle the transactions between the FPGA and the asynchronous memory banks. Each controller is assigned to a specific memory bank, providing a 32-bits synchronous interface through which the data can be accessed for read/write operations. 3.3 Circular Buffers Unit The pixels of each input block are read from memory bank 0 sequentially. During the calculation of the four GLCMs, each pixel in the block is visited five times: First, the pixel is regarded to be the center of a 3×3-pixel neighborhood, and after a number of sequential reads the same pixel becomes non-central in four other 3×3-pixel neighborhoods at 0°, 45°, 90° and 135° directions from the central pixel of each neighborhood. It is noted that the dimension of the neighborhood is 3×3 because the distance between the neighboring pixels for the calculation of the GLCM is d=1. Moreover, only four out of the eight possible neighborhoods are taken into account due to the symmetry of the GLCM. In order to avoid multiple reads of the same pixels, a circular buffers unit has been implemented, reducing the external bandwidth requirements of the proposed architecture. Figure 2 illustrates a part of the input block. The squares in the grid represent the pixels in the block. The pixels marked with diagonal lines are stored in the circular buffer. The circular buffer outputs five pixels, namely the central pixel of the 3×3 neighborhood (black background) and its four neighboring pixels for the four directions (gray background). These 5 pixels are forwarded to the GCUs. As shown in Fig. 2, in every clock cycle (A, B and C snapshots) the last pixel is removed from the circular buffer, the neighborhood is slided by 1 pixel to the right and a new pixel is inserted into the buffer. The circular buffer contains the pixels marked with diagonal lines in every consecutive snapshot. The circular buffers unit contains four circular buffers, one for each input block of W × W dimensions. Each buffer consists of W+3 6-bit cells, as shown in Fig. 2. Through the use of buffering, the external read bandwidth is 4 pixels per Memory Bank 0 Is o la to r C ir cu it Is o la to r C ir cu it GCU GCU GCU GCU VCU